CSP2510CPG

phase-lock loop (PLL) clock driver, 3.3V, 24-TSSOP, 25MHz to 140MHz, –50 mA

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Price:: US $0.75~1.05 / piece [Get Latest Price]

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PartNumber:: CSP2510CPG

Brand:: Integrated Device Technology - IDT | Pack: DIP | D/C: 06+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2012-02-19

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Part Number:CSP2510CPG
US $0.75 - 1.05
STK795-810

US $12.00 - 16.00 / Piece
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LA76810A

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Product Summary

The CSP2510CPG is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The CSP2510CPG is specifically designed for use with synchronous DRAMs. The device operates at 3.3V. One bank of ten outputs provide low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. The applications of the CSP2510CPG include: SDRAM Modules, PC Motherboards, Workstations.

Parametrics

CSP2510CPG absolute maximum ratings: (1)VDD Supply Voltage Range: –0.5 to +4.6 V; (2)VI Input Voltage Range: –0.5 to +6.5 V; (3)VO Voltage range applied to any output in the high or low state: –0.5 to VDD + 0.5 V; (4)IIK (VI <0) Input clamp current: –50 mA; (5)IOK (VO <0 or VO > VDD) Terminal Voltage with Respect to GND (inputs VIH 2.5, VIL 2.5): ±50 mA; (6)IO (VO = 0 to VDD) Continuous Output Current: ±50 mA; (7)VDD or GND Continuous Current: ±100 mA; (8)TSTG Storage Temperature Range: – 65 to +150 ℃; (9)TJ Junction Temperature: +150 ℃.

Features

CSP2510CPG features: (1)Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications; (2)Distributes one clock input to one bank of ten outputs; (3)Output enable bank control; (4)External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal; (5)No external RC network required for PLL loop stability; (6)Operates at 3.3V VDD; (7)tpd Phase Error at 133MHz: < ±150ps; (8)Jitter (peak-to-peak) at 133MHz: < ±75ps @ 133MHz; (9)Spread Spectrum Compatible; (10)Operating frequency 25MHz to 140MHz; (11)Available in 24-Pin TSSOP package.